This invention relates generally to averaging circuits for analog values, and more particularly the invention relates to an active averaging circuit and to an analog to digital converter (ADC) using same.
Conventional high speed, high resolution analog to digital (A/D) converters have used either a full flash or half flash implementation in either CMOS or ECL circuits. The full flash implementation uses 2.sup.N-1 independent comparators and 2.sup.N precision voltage taps to perform a conversion. This type of converter consumes both large amounts of silicon area and power. The half flash implementation uses a two-step, subranging approach to perform a conversion. During the first cycle an M-bit conversion is performed and stored. The data from the first (coarse) conversion is used to determine a subrange for the second N bit conversion. After the completion of the second (fine) conversion, the data from both conversions are combined to give an (M+N)-bit code. This implementation reduces the comparator count to 2.sup.M-1 +2.sup.N-1 which reduces silicon area and power consumption at the expense of lower speed and increased design complexity.
Both the full flash and half flash architectures have several limitations which prevent them from achieving extremely fast and high resolution conversions. They both carry a tremendous amount of redundant information through each conversion cycle since each discrete voltage reference tap has a single, independent comparator associated therewith. Both architectures rely on an extremely large, accurate resistor string to set the discrete reference tap voltages. CMOS implementations generally use a sampling, auto balanced comparator which gives excellent matching, but due to the large number of independent comparators the CMOS implementation sends large, high speed current spikes to both the analog input and the reference taps. These large dynamic transient signals cause severe problems for the user in driving the analog input and quieting the reference ladder taps. The severity of these transient signals is directly proportional to the number of independent comparators. In order to achieve higher speed, higher resolution converters, designers have generally relied upon advances in processing technology using the same design architectures.